Re: final cartridge for vic 20

From: Jim Brain <>
Date: Sun, 6 Sep 2015 11:10:55 -0500
Message-ID: <>
On 9/6/2015 7:03 AM, Nicolas wrote:
> Hi Jim,
> Am 04.09.2015 um 05:11 schrieb Jim Brain:
>> Each bank can be in any 8kB spot of RAM or ROM, and either RAM, ROM, 
>> RO RAM, or nothing can appear in each VIC-20 memory bank. Obviously, 
>> someone needs to write a menu and programmer app...
> this sounds a lot like the Final Expansion 3, with bigger Flash, 
> bigger RAM, but without the sd2iec part.
It is, though I wanted more configurability than the FE3 provided, and I 
also wanted to simplify the registers and not make any assumptions about 
what went where.

I am also using this as a way to learn Verilog, as I have things like 
RAM/ROM (sorry about the extreme delay) that I want to pick back up, but 
want to feel comfortable in my ability to support and cost reduce.


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Received on 2015-09-06 17:00:08

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