Question on Schematic

From: Jim Brain <>
Date: Wed, 18 Feb 2015 22:00:37 -0600
Message-ID: <>
On the EasyFlash 1:

Most of the design looks straightforward, but I am a bit confused by the 
dual F/F going on in the left of the schematic.  Phi2 going high enables 
the flops, and it *looks* like it divides the dot clock to create a 
clock pulse for the latches and the flash ROMs.  Does anyone know why 
someone would go to all that work and not just use the trailing edge of 
Phi2 to latch the data?


Jim Brain

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Received on 2015-02-19 05:00:04

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