On the EasyFlash 1: http://www.c64world.com/ef/assembly/EasyFlash_1.4.1_REV_B.pdf Most of the design looks straightforward, but I am a bit confused by the dual F/F going on in the left of the schematic. Phi2 going high enables the flops, and it *looks* like it divides the dot clock to create a clock pulse for the latches and the flash ROMs. Does anyone know why someone would go to all that work and not just use the trailing edge of Phi2 to latch the data? JIm -- Jim Brain email@example.com www.jbrain.com Message was sent through the cbm-hackers mailing listReceived on 2015-02-19 05:00:04
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