On 04/24/2014 10:51 PM, Groepaz wrote: > On Thursday 24 April 2014, you wrote: >> On 04/24/2014 02:06 PM, David Wood wrote: >>> http://oms.wmhost.com/misc/C64C_VSP-fix_theory.png seems to be the >>> trick. I was linked this via IRC. It doesn't actively search for the >>> party, but instead latches the DRAM address before the VicII has a >>> chance to change its mind. >> >> I see what it does... If I understand it right that trick will only work >> since _CAS on the C64 has to go through the PLA. If _CAS were directly >> connected to the DRAMs, it would fail since the additional delay of the >> 74xx86 and the 74xx573 would cause the DRAMs to miss their column address. >> >> Did someone figure out what exactly happens inside VIC when this problem >> surfaces? > > according to jens schönfeld its a setup-and-hold timing violation. Yes, but why? The CPU was done with its part of the cycle a few hundred nanoseconds before this problem happens. What can the CPU do to VIC there that will only surface that much later? I would expect that no matter what the CPU does, everything inside VIC had stabilized by then. Gerrit Message was sent through the cbm-hackers mailing listReceived on 2014-04-25 15:01:05
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