Re: Interesting programming description for bank selection

From: Marko Mäkelä <>
Date: Sat, 19 Apr 2014 11:05:23 +0300
Message-ID: <20140419080522.GA4186@x220>
On Sat, Apr 19, 2014 at 02:39:59AM -0500, Jim Brain wrote:
>Page 4 is the circuit
>>The NOPs are to allow enough time for the page number to appear on the 
>>data buss before you transition pin 12.

>That doesn't make any sense to me.  On the bus, I would assume the 
>first sequence would be:

To me neither. On Page 4, there is a 10µF capacitor (C3) between the CLR 
input and ground, for the system reset signal. That looks strange, 
because the capacitor on the Vcc line is smaller ("C2.1uf"), I guess 
meaning "C2" and "0.1µF".

I wonder if a capacitor C1 is missing on the CLK input. I would have 
expected a "hack" in the circuit to adjust the pulse timings. AFAIU, the 
resistors and the transistor alone are not going to cause that much 


You forgot that NOP ($ea) takes 2 clock cycles. On the data bus, it 
should probably look like 3 $ea and 2 $8d, instead of 2 $ea.

Anyway, the STA $d700 should be 4 clock cycles like you say, only 
writing the data on the last clock cycle. If you want 2 successive 
writes, you can use a read-modify-write instruction. But, that would 
require a read to deliver valid data before the two writes.


PS: Your choice of the word "interesting" made me think of the 
"Anglo-Dutch Translation Guide" in the article

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Received on 2014-04-19 09:00:08

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