On 11/03/2014 7:55 PM, email@example.com wrote: > ------------------------------------------------------ > From: Clockmeister >> >> On 11/03/2014 4:30 AM, firstname.lastname@example.org wrote: >>> When trying to deal with some 4168 XRAM chips, I couldn’t get them to work properly. After >> studying the datasheet I found in the notes: >>> http://dl.dropboxusercontent.com/u/58002657/4168_notes.jpg >>> >>> Point [2.] seems important to me but I seem to have problems interpreting it unambiguously.. >> or for some other reasons these RAMs still don’t want to work.. >>> “An initial pause of 2ms is required after power up, followed by any 8 _CE cycles and 64 >> _RFSH cycles before proper device operation is achieved. Read, write, and external >> refresh cycles may be used as _CE dummy cycles for initialisation. The 64 refresh dummy >> cycles can be performed before or after the 8 _CE dummy cycles. Both dummy cycles must >> be within AC parameters. See figure 1, below." >>> Figure follows as on the picture linked above. How do you understand the above? How should >> it be interpreted? Please note that e. g. here: >>> http://www.smspower.org/uploads/Development/SegaMasterSystemIIServiceManual-1715922A-1.png >>> >>> the _RFSH is tied up to VCC.. >> >> I'm sure I've replaced these with standard SRAM (and/or vice-versa). >> When you say they don't work, what are you trying to get them to work in >> and in what way don't they work? > Some time around the middle of last year I had an idea of doing exactly what you wrote. I wanted to put XRAM in place of SRAM onto my DD2 and DD3 boards because I have a good bunch of those 4168 XRAM chips that lie unused (taken off a working industrial equipment during scrapping). But they don’t work in the sense that the system hangs when I put the XRAM chip. I tried doing the same as on the RAMBOard, i.e. connecting _RFSH to PHI2 and adding one more cap for delaying the _OE/_CE lines. I even connected CS to PHI2 as in the RAMBOard schematic (just to be sure) but it still didn’t help. After scratching my head for a long time I eventually found the note in the data sheet that made me suspicious whether I shouldn’t be doing something extra to make them work.. > > -- > Ok, I follow now. Have you seen this datasheet for the compatible NEC chip? It talks about the different refresh modes (self refresh/Pulse/external refresh). Not sure if it helps though. http://pdf1.alldatasheet.com/datasheet-pdf/view/129893/NEC/UPD4168.html Message was sent through the cbm-hackers mailing listReceived on 2014-03-11 15:00:04
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