Date: 1999-11-18 15:18:23

Hallo Nicholas,

> so how does this work?

As I already packed my books for the "HCC-dagen" starting Friday, I have to do 
it from my head. By (re-)setting a bit in the I/O which the CP/M cartridge 
occupies, you make the DMA line for the C64 (L). At the same time you make the 
/DMAREQ of the Z80 (H) which activates it. That's all. The make sure evrything 
goes smooth, you put some NOPs behind the instruction in case the timing is not 
quit right. The moment you activate the 6510 again, it resumes at the address 
with the I/O-instruction (or a NOP). 
The Z80 starts at $0000, its reset-address, the first time it is activated. The 
rest is the same as with the 6510.

The rest is just a matter of Software.

> re: developing a C64 accelerator, I was just brainstorming again (read as:
> "dreaming").... thought was a scalable processor /cart using an all in one
> PC running a core only emulator (and maybe an REU emu) and writing_all
> /reading_IO via 1MHz DMAs to the real hardware (probably via a set of 8255
> chips on a PCslot or LPT port).... upgrade the PC and upgrade the
> stays the same... unlike the SCPU which is 20MHz until
> someone makes a faster 65816....

I did not completely understand the above. But if I got you right, you want to 
make a device which emulates the processor (and maybe a REU as well)?
I've been thinking about it as well. But I already decided to use normal 
TTL-buffers (74F573 and 74F541) instead of the 8255's. The 8255 only run at 2 
MHz and the buffers can ?? MHZ. The disadvantage is that you have to treat the 
circuit as memory area abd that means much more decoding. The advantage is gain 
of speed and reading/writing 16 bits.

Groetjes, Ruud

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