Hallo allemaal, Last monday I started to analyse the opcodes of the 6502 so I can translate them into steps for the Instruction decoder. I got a lot of help from Marko's docs about this subject. But I still have some questions. Question 1: why do 1-byte-opcodes need two cycles? Instructions like CLC, SEC and CLV only need 1 cycle IMHO. Not to speak of NOP!. The instruction ASL does need 2 cycles (or better 1.5): Opcode Cycle Action Use of internal bus CLC 0H read opcode 1L clear Carry inc PC 1H - 2L - ASL 0H read opcode 1L inc PC ALU-input = A 1H A = ALU-output 2L - Question 2: Why do the ADC- and SBC-opcodes need an extra cycle when in decimal mode? The design of the ALU I have in mind now does not need an extra cycle. But I cannot think of a design which does need this extra cycle. My HW solution (for the moment) of dealing with the branches and indexed opcodes is to add adders to the blocks responsible for the PC and "Temporary Address". Using the ALU would cost too much cycles so I had to come with the above idea. Question 3: If anybody has some other ideas how to deal with branches and indexes and is willing to share them, you at least would make me happy. Any other ideas, comments and remarks are welcome as well. Groetjes, Ruud - This message was sent through the cbm-hackers mailing list. To unsubscribe: echo unsubscribe | mail firstname.lastname@example.org.
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