RE: C128D

From: Bil Herd <>
Date: Wed, 27 Nov 2013 20:48:42 -0500
Message-ID: <>
>Speaking of C128 and C128D, Bil never told us how the synchronisation
problem with the 8563 got fixed in the later revisions. And which 8563 do
>you have in the C128 you just unearthed?

>Also, which revision of the VDC can be considered usable? I have 2 C128,
one of them with a 8563R7A and one with a 8563R9B.

Basically they had a "get with the program" mandate is my memory.  The
head of the chip design department stepped up the pressure for meeting
standards and adding fixes to each rev as they had been moving backwards
at one point.  This also included focus on better testing of the chip as
the Genrad tester was synchronous by nature and couldn't really catch the
problem, especially if the engineer was in denial.

The fix would have been clock synchronization registers/flip-flops, go
through about 4 of them , tiny compared to the size of the problem, and
the error rate dropped from one in 2 seconds to 1 in about 2-3 weeks, very
livable by CBM standards.  (I forget exactly how many 0's in the failure
rate calculation but I remembered the rough time frame).

They also had to fix the output drivers and pre-drivers as the chip could
not turn the first pixel of each line on reliably and also couldn't do
reverse graphics of dark on light, they just couldn't get the line down to
Voltage Low in a pixel time for a single pixel in a cell.  Lots of
capacitance being seen by the driving transistors I think.

Another problem was mine in in that I missed it when I scanned the specs
and agreed to use the part in the 128.  I asked if it was  modeled to
"standards" like the 6845 to which he said yes, so I scanned for
speed-grade and didn't check each and every spec.  So bottom line was it
was modeled after the 6845/65xx bus timings except when it wasn't.  I got
burnt by clock timings related to Phi, as that was really what I was
asking and the chip designer being from a different chip family didn't
understand exactly what I was asking and how important it was.   I
remembered asking Dave Haynie, who had a math and CS degree from Carnegie
Melon if we could use statistical doubletalk to ignore the problem until
the next rev.  The answer was  Quantities like this enforce a
level of honesty all on its own. We did a run of 10,000 over the weekend
to prove whether I was right about the wire on the board fixing a layout
problem that created a standing wave on A10 on the Z80 for example.

Also they had designed the chip to use a production method we didn't have
natively; I believe it was the first CBM chip to use two levels of
ion-implantation density, most chips just used one. I believe he brought
the idea of using it that way with him Motorloa where he had worked on the
68000 and actually had some patents on cell-level stuff.  So my memory is
that we typically used 90-100 "per square" ion density, the ion implanter
was designed for something like 120 per square and the 8563 needed
something like 160 per square.  The chip guys would definitely  have to
back me up on these numbers, been a long time.    The question of the day
for months was "Is the Implanter down?" as it felt the stress of higher
energy (than it was designed for).  We taught people who would have no
idea what this meant to ask the chip guys this randomly; janitors, bar
tenders, etc.


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Received on 2013-11-28 02:00:04

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