Re: The ultimate UltiMax cartridge

From: Gerrit Heitsch <>
Date: Tue, 22 Oct 2013 18:36:36 +0200
Message-ID: <>
On 10/22/2013 05:25 PM, Michał Pleban wrote:
> Hello!
> Gerrit Heitsch wrote:
>> As far as I know, with a 65xx-CPU, you need to incorporate PHI2 into the
>> R/_W signal (R/_W can only go LOW if PHI2 is HIGH), or is this already
>> done inside the MAX?
> Why would I want to do that, when I have a separate /CS signal for both
> chips?

What's the latency in the _CS signal? The delay from the PLA and all the 
gates works the other way too, meaning even though the CPU is done and 
VIC has taken over the bus with AEC, the _CS signal will still be low 
for a time. Doesn't matter with a ROM, but with a RAM that can corrupt a 
write cycle.

There is a reason why all simple 6502 systems I have seen (that includes 
the 1541) gate R/_W with PHI2 when talking to a SRAM.


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Received on 2013-10-22 17:00:03

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