Re: FPGA/CPLD different approach

From: silverdr_at_wfmh.org.pl
Date: Mon, 26 Aug 2013 18:30:55 +0200
Message-Id: <A366ECC5-8F99-4297-837D-53CE8BCA8C85@wfmh.org.pl>
On 2013-08-26, at 16:06, Bil Herd wrote:

> Correct, the Altera line needs an external source to load from

Meaning if I want to have ROM (among other things) inside an FPGA, I need ROM outside first.. :-0
Does one need to "design" the boot process or is it some kind of standard already and the chip "knows" where to get its configuration/content from? 

> (I still call
> it the font but I am probably wrong).  I have done a design were the FPGA
> was $1 and the eeprom was $10, which just sucked.

;-)

> Altera CPLD don’t need to be loaded every power cycle.
> 
> Altera is coming out with flash based devices next year according to the FE
> for my area.
> 
> I usually do away with the EEPROM

Can it be something of small footprint? Like a serial EEPROM?

-- 
SD!
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Received on 2013-08-26 17:02:24

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