Yes a single clock domain is best, only the global clock should appear on the clock input of a flipflop/register and the enable can be applied asynchronously. A lot of floorspace in the bigger FPGA's is dedicated to Phase Lock Loops and support so that the clock domain can be expanded and the same clock domain can extend to the internals of other FPGA's by putting their PLL in a feedback loop of the original. Tweaking for cable and waveguide propagation to realign the clock is also possible using the PLL as a Delay Locked Loop. I did a video system a long time ago that had 24 custom cameras, a DSP engine, and a fiber concentrator, interconnection mesh and there was a single clock that drove the whole thing (Approx 500,000 LE/gates). I used to tap on the TCO knowing that the vibration was effecting the clocks for devices 50 foot in every direction. -----Original Message----- From: email@example.com [mailto:firstname.lastname@example.org] On Behalf Of Mark McDougall Sent: Monday, August 26, 2013 9:44 AM To: email@example.com Subject: Re: 6510FPGA Suggestions? You are completely wrong. The best approach is a fully synchronous design with a clock enable. Sent from my ASUS Pad Istvan Hegedus <firstname.lastname@example.org> wrote: >Hi, > >I have been investigated these cores too and found FPG64's 6510 code >the closest implementation. I am currently playing experiments with it >and one drawback is that it uses fast clock (33Mhz) and slows the CPU >down with the enable signal. This however is needed in order not to >violate the clock domain of the whole FPGA64 design. It can be driven >with slower clock speed too but it is not a good concept to have >different clock speeds in your FPGA. > >http://www.syntiac.com/fpga64.html > >Br >Istvan > > > >-----Original Message----- >From: email@example.com >Sent: Saturday, August 24, 2013 12:41 AM >To: firstname.lastname@example.org >Subject: 6510FPGA Suggestions? > >Since for some time I am walking circles around the FPGA/CPLD >bandwagon, I thought it might be time to have a closer look. I checked >opencores and tried to decide where to spend some money (Altera, Atmel, >Xilinx, ...?) that would be able to implement a 6502 and an I/O port >together with some RAM and ROM modules. My n00b questions to the more >experienced fellows: > >- how many kgates can be needed for something like I mentioned above? >- what would be the best h/w platform/vendor and why? >- what is the most complete/reliable 6502 core to use as starting point? >- what can you suggest or warn about? > >Cordially, > >-- >SD! > Message was sent through the cbm-hackers mailing list > > > Message was sent through the cbm-hackers mailing list 1jj qi Message was sent through the cbm-hackers mailing listReceived on 2013-08-26 15:00:03
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