Re: 6510FPGA Suggestions?

From: Mark McDougall <msmcdoug_at_iinet.net.au>
Date: Mon, 26 Aug 2013 09:43:32 -0400
Message-ID: <w7us4obb39j051rtasf7vwtf.1377524612186@email.android.com>
You are completely wrong. The best approach is a fully synchronous design with a clock enable.



Sent from my ASUS Pad

Istvan Hegedus <hegedusis@t-online.hu> wrote:

>Hi,
>
>I have been investigated these cores too and found FPG64's 6510 code the 
>closest implementation. I am currently playing experiments with it and one 
>drawback is that it uses fast clock (33Mhz) and slows the CPU down with the 
>enable signal. This however is needed in order not to violate the clock 
>domain of the whole FPGA64 design. It can be driven with slower clock speed 
>too but it is not a good concept to have different clock speeds in your 
>FPGA.
>
>http://www.syntiac.com/fpga64.html
>
>Br
>Istvan
>
>
>
>-----Original Message----- 
>From: silverdr@wfmh.org.pl
>Sent: Saturday, August 24, 2013 12:41 AM
>To: cbm-hackers@musoftware.de
>Subject: 6510FPGA Suggestions?
>
>Since for some time I am walking circles around the FPGA/CPLD bandwagon, I 
>thought it might be time to have a closer look. I checked opencores and 
>tried to decide where to spend some money (Altera, Atmel, Xilinx, ...?) that 
>would be able to implement a 6502 and an I/O port together with some RAM and 
>ROM modules. My n00b questions to the more experienced fellows:
>
>- how many kgates can be needed for something like I mentioned above?
>- what would be the best h/w platform/vendor and why?
>- what is the most complete/reliable 6502 core to use as starting point?
>- what can you suggest or warn about?
>
>Cordially,
>
>-- 
>SD!
>       Message was sent through the cbm-hackers mailing list 
>
>
>       Message was sent through the cbm-hackers mailing list
1,jja^qiɚXX
Received on 2013-08-26 14:01:23

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