Re: 8501 datasheet / information is wanted :)

Once Bil Herd has already mentioned how the GATE IN signal works. It is just 
a transparent latch which is responsible for R/W hold off during write 
cycles. He said in the early 264 series prototypes he has used a 6502 CPU 
with external transparent latch as GATE IN.
Despite this, I still have to understand the exact behavior :-)

Istvan

-----Original Message----- 
From: Gerrit Heitsch
Sent: Monday, February 04, 2013 4:45 PM
To: cbm-hackers@musoftware.de
Subject: Re: 8501 datasheet / information is wanted :)

On 02/03/2013 10:48 PM, Gábor Lénárt wrote:
> On Sun, Feb 03, 2013 at 07:50:22PM +0100, Gerrit Heitsch wrote:
>>> The test circuit has UM6502 currently, so
>>> some modification is needed, I guess (I even don't know if 8501 needs 
>>> two
>>> phase clock or not, etc).
>>
>> The 8501 needs only PHI0. But, in order for R/_W to  work properly,
>> you also need to supply a clock signal to the GATE IN pin. In the
>> C16, they use the MUX-signal for that.
>
> Ouch, that's new for me, I mean "gate in". Is there any information how 
> can
> I use that?

I still haven't completly figured out how that signal works, but it has
something to do with the R/_W signal and the variable clock frequency of
the 8501.




> Probably better to
> stay with UM6502 for me, it seems ... There are tons of tips for that for
> creating a minimal 6502 based system, and not so much worth just for an
> on-CPU I/O port, which was the reason I've started to think on this.

Again, the ideal chip for a minimal 6502 system is a 6532 since it will
supply you with lots of I/O, timer and 128 Bytes of RAM. That means all
you need is the 6502, a 6532, an EPROM and possibly one or two 74LSxxx.

  Gerrit





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