On 12/05/2012 03:46 AM, Bil Herd wrote: > The 6502 architecture can suffer in one area in particular with faster > parts on read cycles and that is at the end of the cycle; Fast parts > sometimes are faster to release data and let it go invalid. The '02 > family can require 5-10 ns of hold time which might as well be forever if > you don't have it. If that's the case, then all you'd have to do would be to delay the _CS signal for the Flash through 4 or all gates of 74LS04. Gerrit Message was sent through the cbm-hackers mailing listReceived on 2012-12-05 17:00:06
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