>>> They are not really tristate in the 6502. >> >> This here says otherwise: >> >> http://www.weihenstephan.org/~michaste/pagetable/6502/6502.jpg > > Where is the contradiction? The output (data output register, DOR) is > connected to the external data bus with tristate buffers. Note that > this > is an output. > > OTOH, the predecode register (PD) and input data latch (DL) are always > connected to the external data bus. Thus, they sink any current > that is > on the external data bus. > > Thus, the data bus is not really tristate. A MOS input does not sink any significant current. Typical is 2uA for a normal input, and 10uA for a tristate input (it leaks more via the disabled output driver than via the input itself!) Segher Message was sent through the cbm-hackers mailing listReceived on 2012-09-17 23:00:05
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