Re: RAM replacements

From: Gerrit Heitsch <>
Date: Wed, 12 Sep 2012 21:12:20 +0200
Message-ID: <>
On 09/12/2012 08:56 PM, wrote:
> Hallo Gerrit,
>> The LE-signal for the 74HCT573 is connected to _RAS. The OR-Gate takes
>> _RAS and _CAS as inputs and the output is the _CS signal for the SRAM.
>> In theory, just _CAS should work, but it doesn't, the system crashes,
>> possible due to _CAS being run through the PLA and _RAS going inactive
>> before _CAS does.
>> With the OR-Gate the circuit works.
> I don't understand this. Using an OR gate means that _CS is only
> active LOW when as well _CAS as _RAS are LOW. Then why doesn't _RAS
> alone work?

I can't use _RAS for _CS of the RAM since _RAS will go low and supply 
the first 8 address bits. Those need to be latched. _CAS then supplies 
the second 8 address bits and only when I have those can the RAM become 
active. If I do it before, I'll access (or worse, write to) a location I 
don't want. That suggests using _CAS as the _CS for the RAM.

But I also need _CS for the RAM to go HIGH as soon as _RAS goes high 
because otherwise that will also unlatch the 74HCT573 and have the 
signals on the input appear on the output, resulting in A0-A7 and A8-A15 
being the same. Tends to mess up mostly write cycles from how it looks 
on the screen.

The simplest way to achieve both is to use an OR gate with _CAS and _RAS 
as the inputs. As soon as one of them is HIGH, _CS goes high and the RAM 
goes inactive.

You use an AND if you want to have combine 2 _CS signals so that either 
going low will cause the output to go low. Useful for combining 2 ROMs 
into one larger one (see schematics of the 250469 board and the combined 


       Message was sent through the cbm-hackers mailing list
Received on 2012-09-12 20:00:38

Archive generated by hypermail 2.2.0.