Re: CIAs and PLA in a CPLD?

From: Segher Boessenkool <>
Date: Mon, 3 Sep 2012 06:10:08 +0200
Message-Id: <>
> It depends much on how much extra stuff you want to have in your  
> design. I'm mostly thinking about 5V/3.3V issues. 5V devices are  
> hard to come by these days.

The original devices do not output 5V either (they use NMOS push/pull
totems for output, so the high output voltage is about 5V minus the
enhancement mode threshold voltage).  Have a look at
for some nice plots (thanks Gerrit!)

As you can see, the outputs from the 6569 are about 3.5V, and those
of the 8565 are about 3.4V.

The outputs from the CPU (6502/8500) are a bit higher, 4.0V resp.
4.5V here.

The outputs from the 82S100 are only about 3.6V (and they dip a
bit); the 82S100 is a bipolar device, not MOS.

Finally, the outputs from the big CMOS chip on the newer C64s
is 4.9V or so.

And, of course, you need to get the timing right as well (there is
a significant delay *everywhere*, this is old stuff).

3.3V might actually work better than 5.0V...


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Received on 2012-09-03 05:00:04

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