Re: CIAs and PLA in a CPLD?

From: André Fachat <>
Date: Sun, 02 Sep 2012 02:42:47 +0200
Message-ID: <>
It depends much on how much extra stuff you want to have in your design. I'm mostly thinking about 5V/3.3V issues. 5V devices are hard to come by these days.

Then you have to check the size. The most restricted part is a flip-flop in a CPLD, basically a single register bit. If you look at the CIA, it has at least 16 register bits per port (data + direction), i.e. 32, plus 16 bit latch plus 16 bit counter per timer (IIRC), then there are the shift register, control registers, and internal state bits... So that's way more than 100 bits.
The largest Xilinx 95xx CPLD is the 95108 with 108 so-called cells, with one flip flop per cell (IIRC) - a CIA would not fit in there. A PLA would probably fit into a much smaller CPLD, as it does not use flip-flops. Here the I/O pins are the restriction.

You speak about "both CIAs and PLA" - do you plan to put it into one programmable device? Then I guess you'd need a small FPGA anyway.

Another question is the development environment. One reason I chose Xilinx for my design for example was because the webpack IDE is free and runs on Linux as well.

BTW: a good way to start the development (i.e. before trying to solder those SMD chips yourself, is to get some CPLD or FPGA modules with DIL outlines, like here:


-------- Original-Nachricht --------
> Datum: Sat, 1 Sep 2012 21:59:50 +0200
> Von:
> An:
> Betreff: CIAs and PLA in a CPLD?

> Does anyone have an advice what type of CPLD could be used to implement
> both CIAs and PLA replacement? As I am rather newbie to those, I would like
> to clarify also whether code done for e.g. Chameleon or other projects which
> implemented CIAs already could be reused without problems? I assume it
> depends only (?) on the chip's capabilities/IO pins count and not really on
> the brand/type?
> -- 
> SD!
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Received on 2012-09-02 01:00:12

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