Re: Fun with 6530s and 6532s

From: Christian Dirks <Toast_r_at_IdeaLine.info>
Date: Wed, 20 Jun 2012 12:40:39 +0200
Message-ID: <4FE1A8A7.7010002@IdeaLine.info>
Am 19.06.2012 13:36, schrieb Baltissen, GJPAA (Ruud):
> Hallo Micha,
>
>
>> Generally, if the FPGA is connected to the RESET line, it
>> could re-reset the entire device once it configures.
> The 6530 is indeed connected to the reset line. But...... on a 8250 board this line is driven by a 04 inverter. Pulling the line low could damage the 04. Do you want to risk that?
>
>
The reset from the 04 should not bee needed anymore then and could be 
disconnected, or am I wrong ?

-- 
Christian Dirks
Toast_r@Idealine.info



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