I have to admit that I read this and said "really, I thought everything was rally a 2mhz part to do the bus sharing". So I got out my softbound copy of the C128 Programmers Guide and there in my own words that /IOACC will extend the clock cycle. Evidentially the remaining 12 neurons that comprise my memory matrix where the C128 is stored no longer stores enough facts to be accurate. Glad we wrote it down... speaking of which I swear that a word-o-tron could have written better than I did back then, talk about dry, tense changing partial sentences. Lol... one of the women in chip layout taught me to not change from past to future tense in the same sentence.... after the manual was written. So yup, what Garret said. Anyone have a softbound programmers manual in good condition? Mine loses a page every time I pick it up. Bil Herd -----Original Message----- From: email@example.com [mailto:firstname.lastname@example.org] On Behalf Of Gerrit Heitsch Sent: Wednesday, March 07, 2012 12:24 PM To: email@example.com Subject: Re: userport: C64, Plus4, others? On 03/07/2012 10:10 AM, Gábor Lénárt wrote: > For C64 as far as I can guess, an unrolled LDA/STA sequence can cause > something like 7 cycles (for LDA/STA), so on 1MHz it should be around > 140kbyte/sec. Maybe the double with C128 in 2MHz mode (can run CIAs in > C128 with 2MHz clock?). The CIAs in a C128 are 1MHz models and as far as I understand it, even if the CPU runs at 2MHz, the CIAs still run at 1MHz and the CPU clock is 'stretched' to a 1MHz cycle if a CIA (and SID?) access is detected. So running the C128 at 2MHz will make the copy loop faster, but not quite twice as fast. Gerrit Message was sent through the cbm-hackers mailing list Message was sent through the cbm-hackers mailing listReceived on 2012-03-09 16:00:13
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