On 02/28/12 18:42, Ethan Dicks wrote: > On Mon, Feb 27, 2012 at 7:47 PM, Jim Brain<email@example.com> wrote: >> On 2/27/2012 5:42 PM, Ingo Korb wrote: >>> I think you're off by an order of magnitude or two. MOSIS has an online >>> automated quote generator - 30 chips (minimum) in the ON Semi I2T30 process >>> (0.7um CMOS, the largest in the list; no idea if it would be suitable) with >>> 1mm^2 die size (random guess): 158160 USD (including overnight shipping. > If that price is for bare dice, then there's packaging costs to consider, too. Hi, You get a lot of dies from a wafer / 6 wafers / 12 wafers if you use 5V-tolerant process, even if doing just MPW (multi-product-wafer) processing or MPW production. The costs add up from 1) design cost 2) mask cost 3) lead frame, assembly and test 4) shipping. Depending on the fab and the buyer, a 0,25micron mask set can cost from 15kUSD upwards. 0.35 could be fairly economic. Lead frames (for the package) can have startup costs if you can't find anything suitable from the available selection. Test load board and test procedure development costs something. Testing is most simple with all-digital chips when you can use scan test. Analog testing can take considerable tester time, especially if you need to measure small currents (large pull-up or pull-down resistors) or need settling times for analog reference voltages and such. A tester socket can cost 7000usd, and you need a spare. For actual production you need characterization testing (temperatures, voltages), 1000-hour life test etc. But I guess in this case those are not required :-) 160kUSD sounds like a hefty sum, but I guess that could be somewhat reasonable rate for a one-time design+prototype project done as a rush job. If you really start to get reasonably serious about this, make a plan, and we (www.vlsi.fi) can tell you what (if any) is wrong with it. :-) (Btw, we do mixed-signal, i.e. analog+digital on the same chip.) -Pasi Message was sent through the cbm-hackers mailing listReceived on 2012-02-28 23:00:30
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