Re: Disabling memory refresh in UltiMax mode Re: 6510 handling of $00 and $01 registers

From: Gerrit Heitsch <>
Date: Thu, 08 Dec 2011 18:32:48 +0100
Message-ID: <>
On 12/08/2011 03:01 PM, Segher Boessenkool wrote:
>>>> The row address is the low-order 6 bits, right?
>>> Low eight on the VIC-II in the C64 (there is a mask option to make it
>>> low seven, to work with 16k DRAM chips).
>> Right, low 8 on the VIC-II, but I was thinking of the 4164 memory chips.
> Those have eight address pins, which is the row (low) address during
> #RAS, and the column (high) address during #CAS.

The interesting part being that a 4164 needs only a 128 cycle refresh, 
so for the refresh, only the lower 7 bits count. You only need an 8Bit 
refresh counter for 41256 or 41464 DRAMs. In case you need to replace a 
broken 4164 and can't find one, you can use a 41256 instead, just make 
sure Pin 1 (A8) is wired to Vcc or GND.

>> If I remember correctly, I sent the chip to be read. It was from my
>> oldest C64, serial number 32xxx, with ceramic DRAM chips (350ns IIRC)
>> and 6569R1 and so on.
> An antique!

Not only that, but the 6569R1 can be detected by software, at least this 
program can do it:

With a 6569R3 or newer, it will just show '6569', but is somehow able to 
detect the R1 and list it. It is also quite good at detecting the rest 
of the hardware. With some I have no idea how it does it though.

Demos written for the 6569R3 or higher look quite odd on the R1.


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Received on 2011-12-08 18:00:11

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