Re: 6526A synchronous serial behavior?

From: Nate Lawson <>
Date: Mon, 26 Sep 2011 16:28:01 -0700
Message-Id: <>
On Sep 22, 2011, at 6:17 AM, Segher Boessenkool wrote:

>>>> I'm debugging some issues with the 6526A in the 1571 drive running at 2 Mhz. When we try to send a byte to the drive via the shift register, it doesn't always get received properly. This seems to vary from drive to drive. The 6526 does transmit bytes completely reliably.
>>> What frequency signal are you trying to receive?
>> It's 500 Kbit/sec inbound to the 1571.
> I think that should work (just); the datasheet says clock freq / 4.
> That makes sense with how I suspect the circuit works, too.
>>>> I've got a 100 Mhz digital scope and have tweaked the waveform we send, just to see what works. It seems that the drive receives the data most reliably when SRQ is on an uneven duty cycle (say 30% low, 70% high). It's still never 100% reliable though.
> Maybe it's like the 6522's CB problem?  Changing the signal near the
> phi2 falling edge isn't always detected (we don't quite know why).
>> Or have a 6526 schematic? If it is just sampling CNT on every Phi2 rising edge, for example, that could explain this issue.
> I expect it to be a static transparent latch on phi2 (so it latches
> on the falling edge of phi2, but it's level sensitive, not edge, so
> changes while phi2 is high "shine through" immediately); the output
> of that is compared with the same signal delayed through phi1 and
> phi2 (delayed with dynamic latches), as edge detect.

Thanks for the info. I will do some testing in the next few weeks where I slowly decrease the clock rate and vary the duty cycle to see how the CIA performs. For now, we've released the software that uses this feature to get wider testing. So far, it works for many users.


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Received on 2011-09-27 00:00:04

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