Hi!, On 2011-09-01 23:49, Segher Boessenkool wrote: >> BTW, I thought that these internal rams were in fact 40-stage shift >> registers (2x8) with feedback paths. ... > > On the VIC-II, it really is a standard SRAM. The row select is a > shift register though. > > It's handled by a few different state machines: the BA/AEC/bus access > thing handles when the VIC-II will actually put addresses on the bus. > It's conservative: if it starts too late, it gets bad data, too bad. > Actually putting something on the address lines is a separate thing, > for the video matrix that's a binary counter with reload. And the > data lines thing is separate as well: data from the pins is driven > on the RAM columns when fetching character pointers; on the other side > of the RAM, the columns are read out (whether the RAM is currently > being written or not). Finally the character bitmap data is handled > separately as well: it is fed through a little queue, so the X soft > scroll will work (the memory access pattern is totally fixed wrt it). Thanks for the info. So, if I get that correctly, the temporary space is in fact sram, yet, the active row is selected by a shift register (ie. a single bit in a shift register). Also, as this is really sram, I suppose, only one cell ("address") of the bank can be accessed at a time, whether written or read (or both). BTW, what do you know about how the VIC-II handles attribute data? I mean: the character pointer fetch / character mask fetch / display mechanism looks to work straightforward (current character pointer byte is taken from the internal ram bank, whether the cell is being overwritten or not --> do graphic mask fetch --> mask data is put on some temporary space, from which it is displayed bit by bit (optionally delayed by 0..7 dot clocks, as defined by bit0..3 of $d016). From the other hand, the attribute info needs to be delayed by one cycle (the cycle of graphic data fetch), until it can be displayed. Similarly, even the character pointer data needs to be delayed by one cycle, when the VIC-II is in bitmap mode (ie. the character pointer data is no longer a pointer to the character rom, it's used as attribute info instead, which needs no additional memory fetch). Does the VIC-II have temporary registers for this 1-cycle delay, or does it handle this problem by some other (smart) trick?... > I have no idea about TED badlines, never seen one or programmed one. > Where do I read about it? I'm afraid there aren't any precise docs that describe them in good detail. In principle, they work similarly to those of the VIC-II. In practice, there are a lot of little details, which make the state machine a lot more complicated... probably all due to the fact that the TED has no dedicated color ram, ie. it needs to do two DMA fetches to display a single character row. Levente Message was sent through the cbm-hackers mailing listReceived on 2011-09-02 15:00:08
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