Re: TED badlines, how do they work?

From: Segher Boessenkool <>
Date: Thu, 1 Sep 2011 23:49:26 +0200
Message-Id: <>
> BTW, I thought that these internal rams were in fact 40-stage shift
> registers (2x8) with feedback paths. Normally, the feedback is in
> effect, and the shift registers simply count 40 cycles a row, ie. one
> round. Only a single position (probably at the point of the feedback
> path) needs to be used by the video display logic at a time. Badlines
> simply affect how the feedback path works - if new data is being read,
> the feedback bit would be simply thrown away, and the newly read bit
> used and shifted in. In the case of the Plus/4, the badline logic  
> should
> generally only differ from the VIC-II in how this read / reload logic
> here was implemented.

On the VIC-II, it really is a standard SRAM.  The row select is a
shift register though.

It's handled by a few different state machines: the BA/AEC/bus access
thing handles when the VIC-II will actually put addresses on the bus.
It's conservative: if it starts too late, it gets bad data, too bad.
Actually putting something on the address lines is a separate thing,
for the video matrix that's a binary counter with reload.  And the
data lines thing is separate as well: data from the pins is driven
on the RAM columns when fetching character pointers; on the other side
of the RAM, the columns are read out (whether the RAM is currently
being written or not).  Finally the character bitmap data is handled
separately as well: it is fed through a little queue, so the X soft
scroll will work (the memory access pattern is totally fixed wrt it).

I have no idea about TED badlines, never seen one or programmed one.
Where do I read about it?


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Received on 2011-09-01 22:00:17

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