On 11/20/2010 10:30 AM, Ruud@Baltissen.org wrote: > http://www.baltissen.org/files/extkernal.pdf > > In a hurry so I hopes things worked out fine. My German is non-existent, but this looks like it's working with delay lines and interpreting some glitch in the addressing. An English translation of the article would help clarify... G1/G2 look to be simple R/C delays, so G8 gets !PHI2(delayed) * BA = !BF I just wish I understood what condition the schematic is looking for. Does ROMH glitch when RAM is due for access as opposed to ROM? Inquiring minds want to know. Jim Message was sent through the cbm-hackers mailing listReceived on 2010-11-21 05:00:02
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