Re: Looking for a VHDL forum or individual help

Date: Mon, 23 Aug 2010 17:10:00 +0200
Message-ID: <>
Hallo allemaal,

André wrote:
> I am using free6502 as CPU core for example.

I spent two hours with Gideon talking about the new 1541Ultimate-II 
and more important (for me), discussing VHDL. It was quite a 
frustrating discussion as most things didn't go the way I thought 
they would: my model wasn't good and the way I had programmed it 
wasn't good as well. The last I can understand; I only have to look 
at the Pascal programs I wrote when I just started programming.
Regarding the model, it is in fact based on my TTl6502. And Gideon 
couldn't detect any flaw :) Using this model I discussed my finding 
that IMHO all the cores I know, including Gideon's, treated NMI as 
level triggered. The docs state that the NMI in the 6502 is edge 
triggered. He agreed with my findings. But so far it never caused 
problems, so why changing it? I gave him an example where things 
could go wrong. Anyway if the docs state edge triggered, why not 
implementing it?

I also discussed the timing around PHI1 and PHI2 and the surprise 
came: it seems that the timing of the 6502 is quite difficult to 
realize in VHDL. But that is no problem as long it is inside a 
complete design like those used for the C-One. So I can indeed 
run in trouble wanting to emulate a real 6502. But I have my ideas 
to circumvent that. Anyway, errorous or not, I will keep on going 
my own way and see where the ship will sink.

   / __|__
  / /  |_/     Groetjes, Ruud Baltissen
  \ \__|_\

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Received on 2010-08-23 16:00:03

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