RE: How to design non-trivial cartridges for c-64?

From: Bil Herd (
Date: 2007-05-27 15:45:59

I saw some description of decoding on a cartridge, let me jump in with
some history:

There are a couple of active low decode lines I/O1 and I/O2 or whatever
they were called.  They decode the bigger base address that says that
the cartridge is most likely being talked to, in the C128 it means the
modes are also correct in addition to the address, in the C64 it mostly
means address.

The problem is that normal design practices is to make these lines a
strobe, meaning that it asserts when the address and r/w line are valid
and de-asserts when data, address and r/w are all valid.  Problem on the
C64 was that the I/O Select lines where not clock qualified, they are
raw decodes which means that the I/O select line might make a couple of
transitions before being asserted or make a couple of transitions and
then NOT assert.  Same at the end of the cycle, there is a very real
glitch as the VIC chip comes online for the next half cycle.

I tried to fix this is C128 by clocking the I/O select line.  We used to
joke about this logic as the difference between chip designers and
hardware types in practice.  I didn't want to know "where" I wanted to
know "true" meaning we like strobe-valid-address type things.

Problem was that third party designers made up their own way of using
the signals based on the C64.  The Speech Cartridge by Carrah actually
used the rising edge glitch on the r/w line to clock in the status of
the I/O select line!

I had to put the glitch back in to be C64 compatible.  So the trick when
designing for the C64 or C128 is you have to not just think of
true-logic but of time, it really is all about the time that data is
valid coming into an event and the hold time that it is valid after the

Common wisdom is to use the 1mhz system clock (PHI) to clock the
trueness, I.E. it becomes the strobe.  Problem is there is nothing that
really says that the address lines are now valid, that happens a certain
amount of time after Phi goes hi as the processor comes on line and the
Vic goes Hi-Z.  Then the I/O decodes will trip, for read purposes this
means that the addresses are valid.  When Phi goes low at the end of the
cycle you know that addresses, R/W line and Data are Valid.  You also
know that Data has been valid a certain length of time in the case or
writes, this is the setup time.  

The area you have to watch is that the data is valid for only a short
period after Phi goes low, known as the hold time.  Holdtimes are as
short as 10-20 ns (shorter if using Phi2) which means that if you have
too much logic in line to create the strobe, the data goes away before
the strobe (took you longer than 10ns to decide to do something).  Rule
of thumb is the strobe has time for only one level of TTL type logic on
anything trying to capture data.  

If you are a read-only device, life is simpler; look for the I/O decode,
knock out some more address lines for granularity, get your data out
there in 100 ns or so and hold it at least 10-15 after the cycle ends,
but then get yer butt off the line.  Also look at the R/W line so that
you don't come on line during a write cycle, shouldn't be needed but
good practice. (There are plenty of stories about blowing up hardware by
tight loops "writing to ROM")

Hope this helps,

Bil Herd

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