From: Ethan Dicks (ethan.dicks_at_gmail.com)
Date: 2007-04-04 20:46:43
On 4/4/07, Anders Carlsson <anders.carlsson@sfks.se> wrote:
> Earlier today, I wrote:
>
> > If it helps, I might try to read them a few times more, perhaps
> > at a lower speed and confirm that I really get consistent output.
>
> No matter speed or how many times I read the chip, the results are
> exactly as I already posted, so no signs of reader inconsistency.
Have you checked the Vcc at the pin on your target EPROMs? To test
erasure and ghosts last year, I rigged up a double-stacked socket with
a tunable voltage divider (pot) so I could turn down Vcc on a 27C256
and watch it behave. I found that using an ultraviolet inspection
lamp (the only thing I had on hand - yes, I know I "need" a proper
lamp, but I didn't have one and couldn't get one for several months),
several hours under the lamp resulted in EPROMs that were blank at
5.00V, but had definite legible bits at 4.80V, and nearly the entire
original contents still visible at 4.60V. At a certain point, the
chip stopped working, but that was, IIRC, below 4.00V.
What I'm wondering is that if you have weak cells _and_ your EPROM
burner/reader isn't giving the full 5.00V, that you might be
witnessing ageing effects from some of the weaker cells (especially
given that you are holding a chip that was burned 24 years ago). The
thought is that seeing one of the columns coming up wrong might be a
case of the reverse of my experiment last year - in your case, not an
intentional erasure being verified, but real data on the threshold of
detectability.
Another option *might* be to push Vcc above 5.00V (while still staying
under the 10% tolerance threshhold) and see if the ROM image "makes
more sense" with respect to bit 3.
Read speed is probably not an issue here, so "slowing down" isn't
likely to help. My initial impulse is to suggest that after 24 years,
some of those insulating wells full of encapsulated electroncs are
drying out. In a few years, there might be nothing legible remaining.
-ethan
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