Re: Re: Clearing EPROMs: How much time to lay in the sun?

From: Ethan Dicks (
Date: 2006-07-18 00:49:56

On 7/17/06, "André Fachat" <> wrote:
> South Pole, You're kidding, or what?

Nope... one of the problems here is that what we have when the last
plane leaves is all we have on hand until late October.

More on the topic of EPROMs, I happened to whip up a simple EPROM
voltage stressor - I sandwiched three machined pin sockets with pin 28
not connected from top to bottom, then stuck a couple of diodes in the
way.  My present rig delivers 4.3 volts to Vcc on the EPROM.

Here's the interesting part... I have 4 EPROMs I recently erased with
a 365nm lamp, 1 for a few hours (maybe a full day), 3 for a few days.
All 4 read 0xFF at a Vcc of +5.0 VDC.  The one that had a shorter
exposure time had garbage that resembled the original contents when
read back at a Vcc of 4.6 VDC.  That same one had 100% readable
strings when read bac at a Vcc of +4.6 VDC.  I'm going to have to
rework the power leads to drop it any further, but I think it'll be a
useful experiment.  I'm probably going to rig it either with a
variable voltage drop (jumpers, etc.) or with a 3.3V regulator to
really give it a workout.  Before I complete the modification, where's
a good place to stop?  3.3V?  Higher?  I mostly am doing this with
27C256s of various brands (they are old 486 BIOS chips).

Thanks for the information about how improper erasing surfaces.  I
wouldn't have known to test this without this thread.  Anyone else
have any ideas?


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