From: Spiro Trikaliotis (ml-cbmhackers_at_trikaliotis.net)
Date: 2005-04-01 12:31:19
Hello Uz,
* On Thu, Mar 31, 2005 at 11:45:53PM +0200 Ullrich von Bassewitz wrote:
> The 65C02 and 65SC02 do not have a Z register. You could read the STZ
> instructions as "store Z register", but originally they meant just
> "store zero". The interpretation as a Z register came with the MOS
> 65CE02 CPU, but I think it was an afterthought, because this register
> is not mentioned in any other CPU doc despite the fact that the 65C02,
> 65SC02 and 65816 all have the STZ instructions.
IMHO, this differentiation is nit-picking. Such a "Store Zero into ..."
is usually implemented inside of the CPU with the help of a Zero
register, which has to be there anyway and which is hard-coded to zero
(thus, in fact, it is not a register but just some lines connected to
GND, but from the microarchitecture's point of view, it behaves like a
register). Thus, "store Z register" and "store zero" are just synonyms
(as long as the Z register cannot be changed).
Or did I miss the point of your statement?
Another thing I do not like in the final draft of the o65 specification:
For the header specification (2.6.1.), you tell that there is
.asc "o65"
When I wanted to interpret (and test) for this, I was not sure if
'o' = $6F (as with ASCII), or
'o' = $4F (as with PETSCII).
Wouldn't it be better to tell
.byt $6f, $36, $35 ; "o65" as magic
so this is non-ambiguous?
Regards,
Spiro.
--
Spiro R. Trikaliotis
http://www.trikaliotis.net/
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