Re: Looking for YMF262

From: Ruud Baltissen (
Date: 1999-07-08 22:41:02

Hallo Richard,

> Can you point me to an ISA bus reference? I'm afraid I know nothing about
> how it works - whether it's multiplexed or not, what the timing of the
> address lines, READ# and WRITE# lines is like, how DMA request and
> acknowledge lines work, etc etc etc

OK. But I'm doing this straight from out my head so you have to forgive me
for any mistake.
The ISA-slot is made out of 62-pins slot and a 43-pins one. The smaller one
is only used for 16-bits operations. The big one has the following lines:
- 20 addresslines
- 8 datalines
- 8 (?) powerlines
- 6 IRQ-lines
- 4 (?) DMA-request-lines
- 4 (?) DMA-acknowledge-lines
- IOR (IO Read)
- IOW (IO Write)
- MRD (Memory Read)
- MWR (Memory WRite)
- AEN (Address ENabled)
- ALE (Address Latch Enabled
- OSC (OSCilator)
- CLK (CLocK)
- EROM/REFR (External ROM/REFResh)

As you already have guesed, the bus is NOT multiplexed. The possible reason
why Richard thought it was is that the first processor used for the PC's, the
8088 or 8086, has a multiplexed bus. The 80286 and higher have, AFAIK, a
normal bus like the 6502.

The behaviour of the address- and datalines can be compared with those of the
6502 as long as one of the four Read/Write-lines is active. The behaviour if
none of the lines is active is not important for our means.
As you can see the bus has a clock but this can NOT be compared with PHI2.
The synchronization task of PHI2 is in theis case performed by the R/W-lines
as well: the rising edge of those lines signals the end of the operation. 
The R/W-line of the 6502 is NOT synchronized with PHI2 so if we want to use
this line for an ISA-card we have to synchronize it. This is were the
74LS139, 2-to-4-multiplexer, comes in place. (Sorry for the typing error).
The 139 combines the PHI2 and R/W-signal and outputs the RD and WR signal.
PHI2 goes to the B-input and R/W goes to the A-input. (Thanks, Nicholas)
These two are enough if you only perform I/O-operations. If you need to
perform Memory-operations as well, you'll need a 138, 3-to-8-multiplexer.
Input C is used to tell what kind of operation is wished.

Memory refresh for the Dynamic RAM on the motherboard and added memorycards
is done by the 8237-DMA-controler. Whether a refresh- or I/O-operation is on
going on is signaled by AEN. AEN = (L) means I/O. In our case simply tie AEN
to GND.

The IRQ-lines are active (H) so you have to connect them to a 65XX-system
thru a 7406 or 74LS05.

CHKRDY, is the NMI-input of the ISA-slot and is active (L). Normally only
used for detecting parity-errors.

IORDY is the RDY-equivalent. Problem: the C64/128 does not have this line at
the expansionport. But I haven't ever seen an I/O-card using this line and
knowing that I/O-operations are performed at about 2+ MHz. this should not be
a problem.

ALE: I know what it does but I don't know its active level anymore. But is
only important for memory-operations above 1 MB.

OSC: 14.31 MHZ. clock. Used for the old Color Graphic Adapter cards.

CLK: the speed of the bus. About 8 Mhz for memory operations.

RESET: active (H)

EROM: With the original XT-motherboard you could overrule the original BIOS
by activating this line. From the AT on it is used to siganl that a refresh
cycle is going on.

DMA-lines: I never have used them for any purpose so I cannot give you any
practical info.

> However, consider the case of C64 plus REU.....
> .
> .
> Are you interested yet? ;)

Hardware projects always have my interrest but at this moment I even am not
able to work at my own projects. So I only can offer you help in the form of
ideas or advise.
Regarding the use of the REU I have some comments:
- Not everybody has a REU :(
- The REU DMAs the data with about 1 MB/sec and this speed cannot be varied.
  44.1 KHz could mean 44.1 KB/sec (or 88.2 KB/sec when stereo). 

- Why not using an original 8237 DMA-controler? 
- Memory could be added by using the idea published by Marko or using a
  74LS160/2 Memory Management Unit. 

I hope this helped a little bit.

Groetjes, Ruud

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