Hallo Andre, > You don't clock the output of the MMU. When you access the MMU in the > lowest bank ($00****), /ME is enabled, but also /CS is also enabled. > From the internal diagram you can see that the /CS input selects the > address lines for the internal RAM. > So what happens is: CPU puts address lines on the bus. The MMU maps > the address lines A12-A23. > When Phi2 goes high, U12 and U9 (in the schematics) enables /CS because > A4-A23 hold the right addresses. > But when /CS goes low, the output of the MMU (without latching) > represent now the register selected with RS0-3 (i.e. A0-3) and not > MA0-3 (i.e. A12-15). Yes, if in MAP-MODE! But the point is to disable the map-mode for that moment. When disabled, MO0..7 are (L) and MO8..11 reflect MA0..3 REGARDLESS the state of /CS. So before (re)programming the MMU I disable the Map-Mode. Simple comme ca :-) Your CS/A65 enables the mapmode the moment you write something to the MMU. But you only can disable it with a reset. Because of that you must preserve the address with a latch. Simple question: If the 612 w/o latch will cause problems IYO, why is it used in the AT and worked w/o any problem??? :-) I hope youunderstand the above is not meant to be a "I'm right, You're wrong discusion". As I intend to build Big-PET using a 612, we soon or later will find out anyway who was right. > As long as the opcodes of the 65816 have the same length in cycles > (6502 emulation) and the clock speed is the same, there is no > problem. > But: when the opcodes take more/less time and/or the clock frequency > is different, there is a problem. Only in software dependent timeloops. > This is the same problem as when you have to use different floppy routines for > 1MHz and 2MHz operation. > > There should not be part-cycle out of phase, as both CPUs should be > coupled by Phi0/Phi2. If the 65816 is clocked at higher speed, it should > be phase-locked to Phi0/Phi2. That I do understand but which Phi0/Phi2; the original one of the PET or the one of the coupled 1541??? Looking at the SCH I notice one important thing: EVERYTHING regarding the diskdrives goes thru the 6522s. So my intuition tells me that using a clock which is out of phase or even a fraction slower or faster won't mess up things. (remember the PET also uses 16 MHz. hmmmm, why not disabling the clock of the 1541 and using the one of the PET???) In case of the C64/128 we have a more serious problem: They run at about 1 MHz.but in both cases the difference is more than a fraction. > One more comment: Is it that useful to use the MMU in the lowest > bank $00****? As far as I know this bank has a special meaning for Stack > etc in the 65816. No. OK, the stack can be place anywhere within Bank 00 but I don't see that as a problem. My mean reason to enable it in Bank 0 is that I can address it using the BASIC or the onboard Monitor of the PET. And both are NOT capable of addressing another Bank. > A second thing: When you clock the 65816 higher, you have to slow down > accesses in the lowest bank as well - the MMU delay is important. Yes, and there does the so called "cripled iMHz." show up. The 65816 starts to present its addresses after the rising edge of the cripled Phi2, and then the MMU starts to presents its addresses. But this proces is loooooong finished before the rising edge of the system Phi2. (At least, that is how I think about it). The moment you run everything at full speed means you only have 125 ns minus the delay time of the MMU. This delay is max.30 ns. This leaves us 95 ns. Using 45 ns. SRAMs I don't think I'll have any problems.... Groetjes, Ruud
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