Re: Big-PET

From: Andre Fachat (
Date: 1998-04-30 18:10:13

Hi Ruud,

> Andre, did you receive the SRCs of the PRGs for the 8x96?

Yes, I got them. Still in the queue...
> Here is another idea of mine: combining the 65SC816 and the 74LS612 in a
> PET. So this doc also contains a lot of tech stuff. I also produced a GIF

Thanks, I got the schematics. One problem, sorry to bug you again
about that:
You don't clock the output of the MMU. When you access the MMU in the 
lowest bank ($00****), /ME is enabled, but also /CS is  also enabled.
>From the internal diagram you can see that the /CS input selects the
address lines for the internal RAM.
So what happens is: CPU puts address lines on the bus. The MMU maps
the address lines A12-A23. 
When Phi2 goes high, U12 and U9 (in the schematics) enables /CS because
A4-A23 hold the right addresses. 
But when /CS goes low, the output of the MMU (without latching) 
represent now the register selected with RS0-3 (i.e. A0-3) and not
MA0-3 (i.e. A12-15). Now the U12 adn U9 disable /CS, and the output
of the MMU changes again, the MMU output becomes the right value 
again, /CS goes low, etc etc

So you should better use the MMU version with latch and use /CS as C input
for example.

> One genearl question remains: What happens if the processor of a PET or
> 1541 runs out of phase with the onboard clock or even at a (slightly)
> different speed? In case of the PET I think of the video and in case of the
> 1541 I think of the I/O for reading from/writing to the disk.

As long as the opcodes of the 65816 have the same length in cycles
(6502 emulation) and the clock speed is the same, there is no
But: when the opcodes take more/less time and/or the clock frequency
is different, there is a problem.
This is the same problem as when you have to use different floppy routines for
1MHz and 2MHz operation.

There should not be part-cycle out of phase, as both CPUs should be
coupled by Phi0/Phi2. If the 65816 is clocked at higher speed, it should
be phase-locked to Phi0/Phi2.

One more comment: Is it that useful to use the MMU in the lowest 
bank $00****?  As far as I know this bank has a special meaning for Stack
etc in the 65816. 

A second thing: When you clock the 65816 higher, you have to slow down
accesses in the lowest bank as well - the MMU delay is important.
But probably I am just to conservative when it comes to timing... :-)


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Andre Fachat, Institute of physics, Technische Universität Chemnitz, FRG

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