From: Spiro Trikaliotis (ml-cbmhackers_at_trikaliotis.net)
Date: 2004-05-13 09:51:49
Hello,
* On Mon, May 03, 2004 at 11:22:04PM +0200 Rainer Buchty wrote:
[... a VHDL description of a 16 bit timer, as I needed ...]
> Way shorter in ABEL, but I'm a bit rusty there... Get yourself a
> webfitter account from Xilinx, upload the design and let the webfitter
> run. 2 Mins later you get a mail that you can download the JEDEC file
> (or need to correct some errors I overlooked due to the late hour).
Thank you (and the others) for your help.
As I feared, my collegues want to go the "simpler" solution, using a
software counter for this. As I mentioned, these solutions seemed to
complex to them, especially since we are not experienced with doing FPGA
designs.
I hope the solution that was decided will work as expected nevertheless.
If someone is interested what this counter is for: Two counters are
needed for every legs of the six-legged robot "LAURON". A picture of it
can be found at
http://www-ivs.cs.uni-magdeburg.de/EuK/Labor/lauron.jpg
We wanted to be able to determine the state of the legs with higher
precision than we are able now.
Again, thank you everyone for your suggestions!
Spiro.
--
Spiro R. Trikaliotis
http://www.trikaliotis.net/
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