From: Marko Mäkelä (Marko.Makela_at_HUT.FI)
Date: 2002-05-02 11:18:12
Hallo Michael,
I'm forwarding your message to the cbm-hackers mailing list, since I
haven't made any experiments with the C128 hardware timing lately.
Several years ago, I experimented with setting both the Z80 flag and
the "64 mode" flag of the MMU simultaneously. (Both live in $d505, if
I remember correctly.) It seemed that both processors would be
activated at the same time. I wanted to write a program that would
execute in the Z80 and the 8502 simultaneously (the addresses and the
data would be wired-anded together all the time, I guess), but I never
found accurate enough information of the Z80.
I'll try answer your specific questions here:
> in fact the i/o chips just pay attention to the adr bus when phi1 is
> H. So some chip has to delay the I/O access by one phi2 cycle... by
> aec or rdy at the 8502?
The VIC-IIe has some sort of input that is activated whenever the
$dxxx I/O area is accessed by the CPU. Something like IOACC. When
the I/O access would occur during the 1 MHz half-cycle that is
normally used by the video chip, the VIC-IIe will halt the processor
clock and postpone the access to the following 2 MHz cycle. This is
just a programmer's view: I don't know if it's done by RDY or by
delaying the processor's clock. It certainly can't be AEC; AEC simply
tristates the address and data bus drivers without halting the CPU.
> Well and now the next question is, how does timing look when the Z80
> accesses I/O ? the /iorqst pin is connected to the PLA so far....
The Z80 has I/O access both via IN/OUT (BC) and via normal
memory-mapped instructions at $d000-$dfff (the mnemonic is LD, if I
remember correctly). I started constructing a Z80-mode memory map in
1995 or so, but I've lost my notes a long time ago. It might have
been that for the IN/OUT instructions, the I/O area is mapped to both
$d000-$dfff and to $0000-$0fff.
Marko
---- forwarded message begins ----
Date: Wed, 01 May 2002 01:53:11 +0200
From: Michael Huth <520052975648-0001@t-online.de>
To: Marko.Makela@hut.fi
Subject: C128 Hardware Timing
Hello,
a friend and me want to use the c128 as computer for controlling an
external measurement computer which can run stand-alone.
So we got interested in the Timing of the C128. Surprisingly there is
nearly no information available.
We used a one ray oscilloscope to look at the clock, aec, ba etc signals.
What we saw was this (use fixed size font):
L = low, H = high, 12 letters are 1µs
phi 1mhz: LLLLLLHHHHHH (call it phi1)
phi 2mhz: LLLHHHLLLHHH (call it phi2)
phi Z80 : LLLLLLHHLLHH (call it phi80)
ok the 1Mhz Timing is well known I think.
at 2Mhz the VIC-II only accesses the Adr.-bus for it's refresh cycles. That
are 5 times after each rasterline when phi 1mhz is L, he takes the adr bus
by setting aec to L
the question I have how does the I/O timing works?
example: the 8502 wants to access the i/o in the first half of phi1 when
phi2 is H, but the I/O is not decoded by the mmu.
in fact the i/o chips just pay attention to the adr bus when phi1 is H.
So some chip has to delay the I/O access by one phi2 cycle... by aec or rdy
at the 8502?
so what chip does stop the cpu for this cycle? (vic or mmu)
if the 8502 wants to access the i/o when phi1 and phi2 is H, there is no
timing problem.
but this timing can work also the way that the cpu really drops to 1mhz for
one phi1 cycle to do the I/O
well and the Z80 timing is even more strange. The Z80A can run at 4Mhz max
and needs a clock timing like HHLL.
above timing shows that C= made it running at 4mhz when phi1 is H, so it is
about 2Mhz overall.
I looked up the Z80 specification and found that it has 2 pins for adress
bus control.
/BUSRQST input, which has to be pulled to low if some external chip wants
to control adr, data bus etc. lines.
/BUSACK output, which is pulled low when the Z80 cpu has gone to it's high
impedance states
both pins are connected to aec and ba and to /z80en (on pla and mmu) with
some logic
So the VIC can tell the Z80 if he wants to access the memory.
But why the hell is the Z80 not clocked in the first half of phi1 ?!?
Because of the vic accesses? Can't be - the VIC can tell the Z80 if he
needs the Bus
(if Z80 would be clocked in phi1 first half, this would make 3mhz clock
when you set Bit4 to 0 in $D011 disabling vic accesses (except refresh &
sprites))
A closer look at the clock shows that the Z80 cycles are shifted somehow:
phi1 : LLLLLLHHHHHHLLLLLLHHHHHH
phi80: LLLLLLHHLLHHLLLLLLHHLLHH
cycle: ------11112222----333344 aso
Well and now the next question is, how does timing look when the Z80
accesses I/O ?
the /iorqst pin is connected to the PLA so far....
Is there any information available?
Ciao....
...Micha
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