On Tue, 8 May 2001, Ruud Baltissen wrote: > Studying the schematic at the end of the PRG, I noticed that the BA-line > running from the VIC to the expansion slot crossed the one running from the > PLA to the AND-gate. Only croosed, _NO_ connection. The schematic diagram at the end of the Programmer's Reference Guide contains many errors. Get a decent schematic diagram from FUNET. > IIRC, the BA-line becomes active some cycles before the VIC tristates the > CPU? Yes, three cycles before. The processor can ignore its RDY input for at most 3 cycles (it cannot perform more than 3 successive writes [when executing BRK or going to process an interrupt]). Marko - This message was sent through the cbm-hackers mailing list. To unsubscribe: echo unsubscribe | mail cbm-hackers-request@dot.tml.hut.fi.
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