Re: 6510 RDY and RESET

From: Michal Pleban <*lists_at_michau.name*> Date: Wed, 4 May 2022 18:31:49 +0200 Message-ID: <b6684ee7-b4c8-4f81-4d80-0df6fe672abd_at_michau.name> · lists_at_michau.name

Segher Boessenkool wrote on 04.05.2022 16:36:

> VEC0 and VEC1 are the signals for the two vector fetches.  As you can
> see, VEC0 is gated by RDY.  The vector isn't fetched while RDY is still
> low.

Thank you. So it appears that I can simply hold the RDY low, then when 
everything is ready pull it high and the CPU will lift its reset vector 
from the ROM in the FPGA.
Regards,
Michau.