Re: 6510 RDY and RESET

From: Michal Pleban <*lists_at_michau.name*> Date: Wed, 4 May 2022 16:51:49 +0200 Message-ID: <2f67b602-d161-6bfc-3950-4c9809b0b29a_at_michau.name> · lists_at_michau.name

silverdr_at_srebrnysen.com wrote on 04.05.2022 15:55:

> Modern FPGAs with built-in flash and Co. are narrowing the initialisation time gap on CPLDs significantly. Unless yours is known to be really slow on this, in the C64 context you may be able have a safe margin before the power-up cycle releases /RESET line[*]. I take this is important only on power-up as during warm RESET your FPGA is already loaded anyway.

I am not sure at the moment if it's going to be a FPGA at all. I may end 
up using a Propeller which is easier to program and cheaper, but 
unfortunately it has around 1.5s startup time.

Regards,
Michau