Re: 6510 I/O port as chip selects to expand memory

From: Jim Brain <brain_at_jbrain.com>
Date: Thu, 18 Nov 2021 15:48:36 -0600
Message-ID: <0f8e6e1c-0a8f-83a3-bfe5-8ebdeb9be92e_at_jbrain.com> 
On 11/18/2021 12:59 PM, Claudio Sánchez wrote:
>>
>
> Why didn't you added lines 6 and 7? It wouldn't had hurt...

Because the goal of the project was the emulate the 6510.  If you want 
6/7, you can simply tweak the Verilog and put two extra pads on the design.

Jim
Received on 2021-11-18 23:00:08

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