Re: Building a 6502 peripheral - timing

On 3/20/2018 1:45 PM, silverdr@wfmh.org.pl wrote:
>
>> In general, if I have a working unit, I run the two systems in parallel, watching the signals for any differences.
> So it is more like trial and error? I thought it was more like measured before and at least coarse-designed to have the same timing.

Not really.  If you can run your project alongside the original unit and 
they both receive the data at the same time, you can then use a second 
CPLD to do the following:

signal A XOR signal B

THen, watch the output of that on a scope or LA.  For something like a 
PLA, that's best.
If the logic you are sure is synchronous, you can do:

flip_flop  ff(.d (A ^B),.clk(CLK),.q(output));

and watch "output" on a LA.  Anytime it is high, it is likely you have 
an issue.
>> Synthetic tools are great to test in general, but Commodore always played fast and loose with the timing.
> That's why we so often need to put efforts into conscious making it behave as it happened to behave for them by chance, right? ;-)
Yes.  Take, for instance, the PLA.  Most newer logic is so much faster, 
so one needs to put delays and such into the line to push the logic 
levels to match the original Signetics part.

>

-- 
Jim Brain
brain@jbrain.com
www.jbrain.com