> On 2018-03-15, at 00:38, Jim Brain <brain@jbrain.com> wrote: > >>> ~WR = !(!(R/!W) * PHI2) >>> ~RD = !(R/!W * PHI2) >> What (exactly) ~WR and ~RD mean? Other that "something" write/read related? And what about _CS? > ~RD means "active low on this signal means a read activity". ~WR is similar. So those are separate lines, right? > _CS is a separate signal on Intel ICs, so no need to worry about it here. It operates the same as with 65/68XX stuff. The reason I worry is because I don't fully understand how a chip with no PHI2 input doesn't "get confused" whether _CS going low means a read or write cycle. What happens when _CS goes low with R_W remaining high and THEN going low, as it seems to be the case with SRAM, when _CS comes first and then comes R_W due to external combination waiting for PHI2? Isn't this what Mia called "spurious short reads"? >> Please bear with me, I am not sure if I make myself clear on that. The general questions are something like "How a peripheral chip should react timing-wise to the incoming signals[*], so that causes no 6502/6510 interfacing problems?". "When should it start driving databus and when to stop doing it on read cycle?". "When should it latch the data bits on write cycle?". "What should be the relation between _CS and R_W?" ... > In general, all addressing and activity signals should be stable before PHI2 goes high. The 64 violates this and some things behave badly. A while back, it was discussed on list why the EasyFlash and the Swiftlink use a 7474 to shorten the phi2 cycle to fix this. > > Assuming PHI2 is the last thing to change, one should place data on the bus during a 65XX/68XX read cycle no sooner than PHI2 going high, and remove after PHI2 goes low > Same for write. The system should latch the data at the end of the cycle (when PHI2 falls). That would imply feeding the chip with PHI2. But memory is not fed with it and still works correctly. -- SD! - http://e4aws.silverdr.com/Received on 2018-03-15 02:00:44
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