Re: Hardware emulation of 6509 using 6502?

Jim Brain wrote:

> You can reprogram the CPLD once it is soldered, but one has to have a
> JTAG programming device (which is not in everyone's toolbox) to do so.
> If you were in the US, just swapping boards to you would be no big deal,
> but your location makes this a bit tougher (Steve is in Canada, I think,
> which is not a ton better, and Andre, not sure, but sure it is not USA :-)

I can buy a Xilinx programmer if the cost is not prohibitive.

> I stack up prototype board designs, since at this time, the cost of the
> board (USD$5.00) is dwarfed by the shipping cost ($30), and shipping can
> be shared among boards. I have 2 other designs, and working on a third.
> Once I have it, I will send off for the units. Anyone who can take a
> look at the schematic and see if I need to push more 6509 or 6502
> signals into the CPLD *need being an operative word. I can see some
> value in pushing a few more high order address lines into the CPLD, to
> allow more granularity in banking, but I want to be mindful of making
> too much change and then having to debug those changes along with the
> original goals.

I looked at your schematic, and I think you might want to connect PHI2
to the CPLD. Right now you have only PHI0 but I am not sure it that's
the right clock to do what we want to do.

Also, with the current schematic, writing to $0 and $1 will also cause
writing to underlying RAM, which should not be a problem normally as the
bank 0 is empty, but maybe it's better not to do it. In this case, you
would want to route R/W signal through the CPLD from 6502 to 6509.

Also, what is the signal N$1, it is labeled on the CPLD but I cannot
find it elsewhere?

Regards,
Michau.

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