Re: Free (as in freedom) FPGA development tools

From: Ingo Korb <ml_at_akana.de>
Date: Fri, 23 Dec 2016 01:33:51 +0100
Message-ID: <u7f6r32mo.fsf@dragon.akana.de> 
silverdr@wfmh.org.pl writes:

> Or any tools that would actually work and let me translate
> synthesizable VHDL designs into GAL JEDEC files.

IIRC Lattice ispLEVER Classic can do that.

-ik

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Received on 2016-12-23 02:00:02

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