> On 2016-04-24, at 11:14, Michał Pleban <lists@michau.name> wrote: > > Another personal opinion here: I did logic synthesis at the university > in both VHDL and Verilog. So after actually using both of them, not just > reading their description, I must say that I would absolutely prefer > Verilog. VHDL requires typing much more to achieve the same effect. > Think about Pascal syntax versus C syntax and you will get the idea. > After you write few hundred lines of "code", you will start appreciating > that. There seem to be a kind of a pattern emerging from what I read around the net: people who begin or do a little / occasionally / hobbyists tend to prefer Verilog as "easier", "more familiar", "more concise". People who do a lot of this / do it for living seem to gravitate towards VHDL. -- SD! Message was sent through the cbm-hackers mailing listReceived on 2016-04-24 16:00:02
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