Re: FPGA/CPLD different approach

From: Michał Pleban <*lists_at_michau.name*> Date: Mon, 26 Aug 2013 14:38:47 +0200 Message-ID: <521B4C57.1050809@michau.name> · lists_at_michau.name

Hello!

silverdr@wfmh.org.pl wrote:

> I understand. What If I forget the CPU emulation and want to build only some RAM, ROM and one or two 8bit bi-directinal I/O ports, all available for the original CPU to interact with - what would you suggest? Can one easily make such structures (RAM, ROM, I/O port) available for 6502 from within a CPLD/FPGA and which would be "better" in such case?

ROM and RAM are costly in terms of re-programmable logic. If you need
these, you will end up using a FPGA anyway.

If you need only I/O, then you can use a CPLD as well, there are still
5V ones available (though more expensive than 3.3V).

Regards,
Michau.

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