On 2013-04-08, at 23:01, Gerrit Heitsch wrote: >>> That's what I meant. Clearing the "screen disable" bit (bit 4 at SCROLY >>> register) is the soft way to get rid of bad lines, used in many timing >>> critical operations. If this bit is (as I expect) cleared on power-up then >>> at least the bad lines are not interfering and there would be no need to >>> monitor the extra line. >> >> its not cleared on reset .... >> > > VIC doesn't have a RESET input pin, meaning it doesn't know that the rest of the system just got hit by the big hammer and will blissfully continue to display what it was programmed to display until the CPU tells it otherwise or the power goes out. > > It should be cleared on power up though, otherwise VIC would display something (colorful junk). It doesn't, you just get a black screen. I am assuming the same. But I can imagine other reasons for it not to display garbage on power-up. -- SD! Message was sent through the cbm-hackers mailing listReceived on 2013-04-08 22:00:53
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