On 2012-10-09, at 17:16, Gerrit Heitsch wrote: > Now, even with the rather late _CS signals supplied by the PLA, the extra few ns of our logic and the added tAcc of the EPROM, the data should still become valid before the end of the cycle. The question is, why isn't it? And to clear that up, a scope or logic analyzer will be needed. I asked friend to send me my Saleae but it will take a couple of days and I shall be leaving again soon so time is precious ;-) -- SD! Message was sent through the cbm-hackers mailing listReceived on 2012-10-09 18:02:13
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