Re: Modern myths

From: Andre Fachat (a.fachat_at_physik.tu-chemnitz.de)
Date: 1999-04-23 11:08:49

William Levak wrote:
> At least that was a coherent description of the circuit.
> 
> I don't see where there is a problem.  We have 3 TTL level chips connected
> together.  Typically a TTL chip output can drive 10 devices.  There is no
> potential for chip failure here.  Remember, these are not unlimited output
> drivers.  for instance, a 74LS20 will output 0.4 milliamps, maximum,
> whereas it's input current is 0.1 milliamps.  The 6522, on the other hand,
> can handle 1.6 milliamps.  If the 6522 is set to input, it will clearly
> pull the signal to it's level, whether high or low.  The signal will then
> either be close to zero volts or five volts.  This signal is fed to a ramp

The Problem is that if that would be true, then the poke would not even
work on the original PET. As I said in the description, in the original 
PET the Sync signal (produced by an LS08) and read by VIA PB5 is fed
to a 74LS20. This LS20 blanks the video signal during off-screen areas.
Would the VIA, if set to output, draw the level to close to 0V, then
the screen would always be completely blank.

Therefore I had a look at the 74LS08 datasheets (see for example
http://www.fairchildsemi.com/pf/DM/DM74LS08.html) and it indeed states
that the chip can source 0.4mA on high output. But when the VIA draws
up to 1.6mA, the LS08 would surely think this is a short circuit, and
happily source up to 20-100mA short circuit current [1]. I guess that's 
more than the VIA can handle. As I said, not a healthy situation.
>From the fact that the LS20 enables the screen as it should we can then
draw the conclusion that the voltage level on the line is 
still above approximately 2V, which is the minimum "safe" voltage
for a "1" (could be less, depending on tolerances, etc. max "0" voltage
is 0.8V). But it may be close.

> generator.  The actual voltage level is not relevant.  all that is
> necessary is that it is high enough to trigger the ramp generator.  The
> ramp generator controls the output to the deflection yoke by a feedback
> network.  You cannot overdrive it.  The only potential problem is to drive
> it at a frequency higher that it is intended for, and thus supplying a
> higher effective power output to the deflection yoke. But, the feedback
> circuit limits this also.  

I don't know much about ramp generators either. But some plausibility
checks:

The VDrive input of the early 8032 schematics (see 
http://www.funet.fi/pub/cbm/schematics/computers/pet/8032/321448.gif
expects 5V for onscreen and 0V for flyback.
As long as the Vdrive input is (much?) higher than 1.93V
a current is simply integrated to get the ramp voltage (see oscilloscope
point (4)) A diode (D602) lets the TTL output draw the charge of C601 and the 
ramp generator goes to 0 when it is time (see oscillscope picture (3) & (4))
The DC voltage at (4) is around 1.93V (so the schematics says). 

Now apply the poke to set Via PB to low output. If
the ramp goes a bit above the 1.93V, and then probably above the
voltage of the TTL level (that might be lower than 5V because the VIA 
draws it) the flyback could be triggered earlier, because the diode
drains C601 much earlier than it should.

> This is about as much as I know about ramp generators.  All I can do is
> repeat what several engineers have said to me.  If you try to run the ramp
> generator at too high a frequency, it will simply not trigger and you will
> get no output.

Don't forget that we have to handle pretty old stuff, no CPUs that 
analyze the video signal and check the timings or so, just simple
analog electronics. Probably you could ask those engineers to 
analyze this analong circuitry with the schematics?

Later (see 
http://www.funet.fi/pub/cbm/schematics/computers/pet/8032/8032034.gif)
the analog electronics has been replaced by an integrated circuit,
a TDA 1170. This could probably handle the reduced Vsync voltage.

Andre

[1] Only one pin and not longer than a second, otherwise....

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Andre Fachat, Institute of physics, Technische Universität Chemnitz, FRG
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