From: Hársfalvi Levente (hlpublic_at_freestart.hu)
Date: 2004-11-03 16:48:21
Hi!, > I'm not sure how you'd determine the "overflow" cycle count. The first > IRQ is the detection of the falling edge of the POT line. I tried the > latter approach, which would reduce jitter to 3 cycles, but wasn;t > having much luck. However, I looked at my code, and I'm essentially > doing the same thing, so I'll try it again. Hmmm, I had some ideas but I wasn't sure, so I rather downloaded the Mega8's datasheet first ;-) So... As I see, the input capture event can't reset the 16 bit counter... instead, 1.) it captures the current value of t1 to a pair of registers, 2.) it can generate interrupts. Given that, I'd use the following method: -- The interrupt that starts the cycle would be the input capture interrupt and -pin. -- When the interrupt occurs, the current timer value is captured. When the interrupt routine is (finally) executed, the current value of the (still running) timer is known to the interrupt routine. Thus the additional delays are known to the interrupt routine. -- I'd subtract the captured value from the current value (which will be always positive). Add a calculated (or experimental) static offset value, then write the value to t1. Although the interrupt itself won't be cycle exact, the value in t1 will be. It's also worth mentioning that the AVR has some mechanisms to handle the otherwise async 16-bit registers (one of the 8-bit values is captured to a tmp register upon the read or write of the other 8-bit part). -- I'd use the output capture capability of t1 to pull the outputs high at the right minute. For that, only the OCR registers must be set. Some tweaking might be needed around this part (not this task itself, but the other half, where the outputs are turned back to 0). Still, as the timer itself is cycle exact, nothing but the first interrupt (the "zeroing" of t1) would have to be cycle exact (like above). -- The fact that t1 itself is kept alone for the whole process gives another possibility: at the end, or better said, at the start of the next full cycle, the value captured by the ICP event is the exact value, measured in the AVR's clock, of the SID's 512 clock cycle time (which in this case is delivered without any extra effort :-) ). L. Message was sent through the cbm-hackers mailing list
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